Enfance et identité

Après une ébauche de définition actuelle des mots « enfance » et « identité », nous partirons de la Convention Internationale des Droits de l'Enfant, dite Convention de New York (20 Novembre 1989). Ce texte définit toutes les situations d'enfants (de 0 à 18 ans), leur identité et la place qui leur revient dans l'organisation d'une société moderne. Pour en comprendre le sens et l'évolution, nous emprunterons « La longue route des droits de l'enfant de Janusz KORCZAK à Françoise DOLTO, en passant par TOMKIEWITCZ », depuis la Société des Nations en 1924 (première déclaration des droits de l'enfant) jusqu'à 1959, pour arriver à celle de New York. Ce texte original n'est pas seulement un texte juridique, éducatif, psychologique, il se sert des connaissances de la fin du XXe siècle pour élaborer des normes universelles de droit pour les mineurs. Enfin, nous ébaucherons, en conclusion, les dérives que ces diverses dispositions ont connues, oubliant le préambule implicite de ce texte: « Une place pour chacun, à chacun sa place! »

3D ICs: An Opportunity for Fully-Integrated, Dense and Efficient Power Supplies

International audienceWith 3D technologies, the in-package solution allows integrated, efficient and granular power supplies to be designed for multi-core processors. As the converter design obtains few benefits from the scaling, 3DIC allows the best technology to be chosen i.e. one which suits the DC-DC converter design. This paper evaluates the achievable power efficiency between on-die and in-package converters using a combination of active (28 and 65nm CMOS nodes) and passive (poly, MIM, vertical capacitor) layers. Based on the same load power consumption, on-die and in-package switched capacitor converters achieve 65% and 78% efficiency, respectively, in a 1mm 2 silicon area. An additional high density capacitance layer (100nF/mm 2) improves efficiency by more than 20 points in 65nm for the same surface which emphasizes the need for dedicated technology for better power management integration. This paper shows that in-package power management is a key alternative for fully-integrated, dense and efficient power supplies

Power gain estimation of an event-driven wake-up controller dedicated to WSN's microcontroller

International audienceTo deal with Wireless Sensor Node's energy constraints , new architectural solutions have to be found. This paper proposes to analyze a WSN microcontroller subsystem power consumption to extract the main power contributors according to different applicative execution phases. The objective is to come out with the energy reduction potentiality offered by an additional module called Wake-Up Controller. This block is able to substitute to the main CPU for current tasks like data transfers between sensors, memories or radio and fine grain power/frequency management of the entire node's sub-modules. Power simulations of a microcontroller subsystem based on FDSOI28 technology, with and without the Wake-Up Controller use, are proposed. Results are presented for applicative scenarios ranging from very low to high activity rates. This study exhibits power gains from 14.5% to 76% in the full range attesting the future design of this new module

Fast and Accurate TLM Simulations using Temporal Decoupling for FIFO-based Communications

International audienceUntimed models of large embedded systems, generally written using SystemC/TLM, allow the software team to start simulations before the RTL description is available, and then provide a golden reference model to the verification team. For those two purposes, only a correct functional behavior is required, but users are asking more and more for timing estimations early in the design flow. Because companies cannot afford to maintain two simulators for the same chip, only local modifications of the untimed model are considered. A known approach is to add timing annotations into the code and to reduce the number of costly context switches using temporal decoupling, meaning that a process can go ahead of the simulation time before synchronizing again. Our current goal is to apply temporal decoupling to the TLM platform of a many-core SoC dedicated to high performance computing. Part of this SoC communicates using classic memory-mapped buses, but it can be extended with hardware accelerators communicating using FIFOs. Whereas temporal decoupling for memory-based transactions has been widely studied, FIFO-based communications raise issues that have not been addressed before. In this paper, we provide an efficient solution to combine temporal decoupling and FIFO-based communications

Architecture and Control of a Digital Frequency-Locked Loop for Fine-Grain Dynamic Voltage and Frequency Scaling in Globally Asynchronous Locally Synchronous Structures

International audienceA small area fast-reprogrammable Digital Frequency-Locked Loop (DFLL) engine is presented as a solution for the Dynamic Voltage and Frequency Scaling (DVFS) circuitry in Globally Asynchronous Locally Synchronous (GALS) architectures implemented in 32 nm CMOS technology. The DFLL control is designed so that the closed-loop system is able to cope with process variability while it rejects temperature changes and supply voltage slow variations. Therefore the DFLL is made of three main blocks, namely a Digitally Controlled Oscillator (DCO), a "sensor" that measures the frequency of the signal at the output of the DCO and a controller. A strong emphasis is set on the loop filter architecture choice and the tuning of its parameters. An analytical model of the DCO is deduced from accurate Spice simulations. The delay introduced by the sensor is also taken into account to design. From these models, an optimal and robust controller with a minimum implementation area is developed. Here, "optimal" means that the controller is computed via the minimization of a given criterion while the "robustness" capability ensures that the closed-loop system is tolerant to process and temperature variations in a given range. Therefore, performances of the closed-loop system are ensured whatever the system characteristics are in a given range

A 3D IC BIST for pre-bond test of TSVs using Ring Oscillators

International audience3D stacked integrated circuits based on Through Silicon Vias (TSV) are promising with their high performances and small form factor. However, these circuits present many test issues, especially for TSVs. In this paper we propose a novel Built-In-Self-Test (BIST) architecture for pre-bond testing of TSVs in 3D stacked integrated circuits. The main idea is to measure the variation of TSVs capacitances in order to detect defective TSVs. The BIST architecture is based on ring oscillators, frequencies of which depend on TSVs capacitances. The proposed BIST is integrated within the JTAG standard. This paper presents spice simulation results and logic synthesis results of the proposed TSV ring oscillator structure using a 65 nm CMOS technology, including 10 μm diameter TSV middle technology. Due to local process variations, the proposed test architecture is limited in accuracy; it detects only large capacitive faults on TSVs

A simulation framework for rapid prototyping and evaluation of thermal mitigation techniques in many-core architectures

International audienceModern SoCs are characterized by increasing power density and consequently increasing temperature, that directly impacts performances, reliability and cost of a device through its packaging. Thermal issues need to be predicted and mitigated as early as possible in the design flow, when the optimization opportunities are the highest. In this paper, we present an efficient framework for the design of dynamic thermal mitigation schemes based on a high-level SystemC virtual prototype tightly coupled with efficient power and thermal simulation tools. We demonstrate the benefit of our approach through silicon comparison with the SThorm 64-core architecture and provide simulation speed results making it a sound solution for the design of thermal mitigation early in the flow

Power Gain Estimation of an Event-driven Wake-Up Controller dedicated to WSN's Microcontroller

Abstract-To deal with Wireless Sensor Node's energy constraints, new architectural solutions have to be found. This paper proposes to analyze a WSN microcontroller sub-system power consumption to extract the main power contributors according to different applicative execution phases. The objective is to come out with the energy reduction potentiality offered by an additional module called Wake-Up Controller. This block is able to substitute to the main CPU for current tasks like data transfers between sensors, memories or radio and fine grain power/frequency management of the entire node's sub-modules. Power simulations of a microcontroller sub-system based on FDSOI28 technology, with and without the Wake-Up Controller use, are proposed. Results are presented for applicative scenarios ranging from very low to high activity rates. This study exhibits power gains from 14.5% to 76% in the full range attesting the future design of this new module

3D advanced integration technology for heterogeneous systems

International audience3D integration technology is nowadays mature enough, offering today further system integration using heterogeneous technologies, with already many different industrial successes (Imagers, 2.5D Interposers, 3D Memory Cube, etc.). CEA-LETI has been developing for a decade 3D integration, and have pursued research in both directions: developing advanced 3D technology bricks (TSVs, µ-bumps, Hybrid Bonding, etc), and designing advanced 3D circuits as pioneer prototypes. In this paper, a short overview of some recent advanced 3D technology results is presented, including some latest 3D circuit's description